Electronics

MOSFET & CMOS Logic

A metal plate over an insulator, close enough to a slab of silicon to pull a conducting channel into existence underneath. Nothing crosses the insulator, so control costs no current, and that is why a chip can hold billions of these. Stack a p-type over an n-type and you have an inverter.

In the device view the channel appears only above threshold; in the gate view, click an input on the schematic to flip it

Drain current—

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View

Type

Curve

Gate voltage V_GS 2.00 V

no channelwide open

Drain voltage V_DS 1.20 V

a plain resistorpinched off

Threshold V_th 1.00 V

Width over length W/L 1.00

Values

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What to observe

With no gate voltage, source and drain are two diodes back to back and nothing flows. Past V_th the gate pulls an inverted layer of carriers under the oxide, and the depleted region stops growing because that layer screens it.
With a small drain voltage the device is a resistor set by the gate(triode). Raise V_DS past V_GS − V_th and the channel pinches off: the current levels out and the carriers speed up where the channel thins.
In the logic gate, sweep A by hand. The supply current is zero at both ends and spikes only mid-transition, when both transistors are on: that is why idle CMOS costs almost nothing.
In NAND the pull-up is the dual of the pull-down: two nMOS in series below, two pMOS in parallel above, so the output falls only when both inputs are high.

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