MOSFET & CMOS Logic

What to observe

1. Start with the gate voltage at zero. Source and drain are two n-type islands in a p-type sea, so whichever way you push, one of the two junctions is backwards and nothing flows. A MOSFET with no gate voltage is not a bad conductor, it is two diodes back to back.
2. Raise the gate. Nothing crosses the oxide, but the field through it drives holes away and, past V_th, pulls enough electrons up against the underside of the insulator to invert that layer into n-type. A conducting bridge appears between source and drain that was not there a moment ago, made of carriers borrowed from the substrate.
3. With the drain voltage small, the channel is an even sheet and the device is an honest resistor whose value you set with the gate. That is the triode region, and it is why a MOSFET makes a good switch: fully on, it is just a small resistance.
4. Now raise the drain. The channel is thinner at the drain end, because what holds it open there is V_GS − V(x), and V(x) has climbed. Push until V_DS = V_GS − V_th and the channel pinches off at the drain. Past that, extra drain voltage falls across the pinched gap instead of the channel, the current stops growing, and the device becomes acurrent source controlled by the gate. Watch the carriers speed up as the channel narrows: same current, less room.
5. Look at the shape of the channel itself. Current is the same at every point along it, so where the layer is thinner the carriers must move faster, and you can see them do it. The taper is not a decoration, itis the reason the saturation current goes as the square of the overdrive.
6. Switch to the logic gate. The p-type transistor turns on when its gate is low and the n-type when it is high, so exactly one of them conducts. The output is either tied hard to the supply or hard to ground, never both and never neither, which is what makes the levels restore themselves instead of degrading down a chain.
7. Sweep the input by hand and watch the supply current. It is essentiallyzero at both ends and spikes only in the middle of the transition, where both transistors are briefly on together. That single fact is why CMOS won: a circuit that is not switching costs almost nothing, so you can afford to put billions of them on one piece of silicon.
8. Try NAND and NOR. The pull-down network is the logic you want and the pull-up is its dual: series where the other is parallel. Two nMOS in series conduct only when both inputs are high, so the output only falls then, which is NAND. Nobody had to design the top half separately.